A wafer for a semiconductor device has been known that includes a silicon base, an oxide layer stacked on the silicon base, a lower resist layer formed on the oxide layer of an organic layer, and a bottom antireflective coating layer (“BARC layer”) formed on the lower resist layer. In particular, the lower resist layer serves as a mask when the oxide layer is etched.
As the size of a semiconductor device recently decreases, it is required to more finely form a circuit pattern on the surface of a wafer.
To form such a fine circuit pattern on the wafer, it is needed to precisely transcribe a small size of opening portion (hole or trench) to the target layer, i.e., oxide layer, as well as to make the minimum size of the pattern smaller in the lower resist layer serving as a mask layer in manufacturing the semiconductor device.
The opening dimension of hole or trench (hereinafter, simply referred to as “hole”) becomes smaller and an aspect ratio thereof becomes greater, while the thickness of the mask layer tends to be thin. This may cause striations at the top portion of the hole and distortions at the bottom portion. In the meanwhile, since mask layer of a sufficient thickness cannot be secured upon etching, a bowing shape (swollen or expanded shape) may occur at the cross section of the hole formed in the target layer. These may deteriorate the throughput of semiconductor devices.
Conventionally, Japanese Patent Application Publication Nos. 2004-119539 and 2001-110784 disclose a technology to prevent hole shape from being deformed or distorted.
Japanese Patent Application Publication No. 2004-119539 is directed to preventing exposure of side walls of a pattern-etched dielectric film to O2 plasma and discloses an ashing method of a resist pattern that includes removing a resist pattern employed as a mask layer in the pattern etching of an interlayer dielectric by an ashing process through the supply of O2 plasma, wherein the ashing process is performed while the supply of carbon and O2 plasma is performed at the same time.
Japanese Patent Application Publication No. 2001-110784 is directed to an etching method of obtaining a vertical fabricated shape having less bowing when a dielectric layer is processed in manufacturing a semiconductor device wherein the incident amount of O, F, or N radicals excessive at the beginning of etching is adjusted or suppressed by controlling the gas flow rate or the amount of O, F, and N consumed at inner walls together with the etching time, to thereby obtain a stable etching shape.
However, the above-mentioned prior arts focus on making even the top shape of the hole formed in the target layer, and thus fail to show a satisfactory result in removing a distortion of the cross section of the hole. Moreover, it is also unsatisfactory to suppress occurrence of a bowing at the cross section of the hole.